VHDL CODE OF ADDER /SUBTRACTOR

an adder/subtractor circuit ,as the name indicates ,is able to perform addition as well as subtraction.Here ,I used 4 bit addition and subtraction units together.(Such a circuit is available in the market. It is 7483).Here ,I have a control signal as input ,in addition to the conventional inputs.Here,when the control signal is '0' addition takes place.When control signal is '1',subtraction takes place.The control signal is represented as ADD_SB.Now consider the logic diagram shown below.If you are not familiar with the design of this circuit,please refer any standard text book of Digital Electronics.



Now consider the VHDL code
--FIRST START WITH A FULL ADDER
--THEN DESIGN XOR GATE
--THEN BIND 4 FULL ADDERS AND 4 XOR GATES
--PURE STRUCTURAL MODELING
--MIXED OR BEHAVIORAL ALSO CAN BE USED
--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;
--I AM GOING TO DESIGN AN ENTITY FOR XOR FUNCTION
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XOR_1 IS
PORT(A,B:IN STD_LOGIC;Y:OUT STD_LOGIC);
END XOR_1;
ARCHITECTURE BEHV OF XOR_1 IS
BEGIN
Y<=A XOR B;
END BEHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADD_SUB IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);AD_SB:IN STD_LOGIC;SUM_DIF:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT :OUT STD_LOGIC);
END ADD_SUB;
ARCHITECTURE BEH123 OF ADD_SUB IS
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C_TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
XOR1:ENTITY WORK.XOR_1 PORT MAP(B(0),AD_SB,TEMP(0));
XOR2:ENTITY WORK.XOR_1 PORT MAP(B(1),AD_SB,TEMP(1));
XOR3:ENTITY WORK.XOR_1 PORT MAP (B(2),AD_SB,TEMP(2));
XOR4:ENTITY WORK.XOR_1 PORT MAP (B(3),AD_SB,TEMP(3));
-- INV1:ENTITY WORK.INV PORT MAP (AD_SB,CTRL);
--ADDER:ENTITY WORK.ADDER_4BIT PORT MAP(A,TEMP,SUM,COUT);
FA1:ENTITY WORK.FA PORT MAP (A(0),TEMP(0),AD_SB,SUM_DIF(0),C_TEMP(0));
FA2:ENTITY WORK.FA PORT MAP (A(1),TEMP(1),C_TEMP(0),SUM_DIF(1),C_TEMP(1));
FA3:ENTITY WORK.FA PORT MAP (A(2),TEMP(2),C_TEMP(1),SUM_DIF(2),C_TEMP(2));
FA4:ENTITY WORK.FA PORT MAP (A(3),TEMP(3),C_TEMP(2),SUM_DIF(3),COUT);
END BEH123;