VHDL MODEL OF FULL ADDER

A full adder has 3 single bit inputs and two single bit outputs.The outputs are sum and carry respectively.From truth table ,we can obtain the logic expression for the sum and carry output.Here I used the logic expressions.We can also use structural style of modeling by using gates.



The VHDL code of full adder unit is shown below.

--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;