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Thursday, February 25, 2010

MODEL OF D FLIP FLOP

Flip flops are memory elements,which can store a bit.D flip flop is useful in designing counters,shift registers etc.Here D stands for data.It is a synchronous circuit.So it need a clock signal for working.A simple block diagram of D flip flop is shown below.it will help you to understand the list of inputs and outputs needed for the operation of it.




The inputs needed for operation are:
1)D :This input is the actual data input to the flip flop.
2)CLOCK :This is the clock needed for all synchronous circuits.
The outputs needed are:
1)Q :This is the first output of D flip flop.On the active edge of clock(for edge triggered flip flops) the D input is transferring to this output pin.
2)QBAR :This gives the complement of Q.

Working: In my design ,I developed a positive edge triggered flip flop. That is,the D input is transferring to Q during the '0' to '1' (or low to high)transition of CLOCK> If you need a negative edge triggered flip flop ,you can edit this code by replacing RISING_EDGE(CLOCK) by FALLING_EDGE(CLOCK).

VHDL CODE OF D FLIP FLOP

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF_1 IS
PORT(D,CLOCK:IN STD_LOGIC;Q,QBAR:OUT STD_LOGIC);
END DFF_1;
ARCHITECTURE FF OF DFF_1 IS
BEGIN
PROCESS(D,CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
Q<=D;
QBAR<=NOT D;
END IF;
END PROCESS;
END FF;
--IT IS WORKING PROPERLY

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