Google Search

Loading...

Saturday, February 27, 2010

VHDL MODEL OF 4 BIT PARALLEL BINARY ADDER

A 4 bit binary parallel adder can be formed by cascading four full adder units.The carry of each stage is connected to the next unit as the carry in (That is the third input).Similarly we can make 8 bit adder.Remember 8 bit adder is a significant design ,because we need it in processor design as part of ALU.(There is no need to use this structural style model there.Instead, we can use the packages available in VHDL directly).A simple logic diagram of 4 bit parallel binary adder is given below.



The VHDL code of 4 bit parallel adder is given below

--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;
-- NOW DESIGN A 4 BIT ADDING UNIT BY CASCADING 4 FULL ADDER UNITS
--STRUCTURAL BINDING OF UNITS ENTITY FA
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADDER_4BIT IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);C:OUT STD_LOGIC);
END ADDER_4BIT;
ARCHITECTURE BEHV OF ADDER_4BIT IS
SIGNAL TEMP:STD_LOGIC:='0';
SIGNAL CAR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
FA1:ENTITY WORK.FA PORT MAP(A(0),B(0),TEMP,S(0),CAR(0));
FA2:ENTITY WORK.FA PORT MAP(A(1),B(1),CAR(0),S(1),CAR(1));
FA3:ENTITY WORK.FA PORT MAP(A(2),B(2),CAR(1),S(2),CAR(2));
FA4:ENTITY WORK.FA PORT MAP(A(3),B(3),CAR(2),S(3),C);
END BEHV;
--getting output properly
--DIRECT INSTANTIATION IS USED

No comments: