VHDL CODE OF ADDER /SUBTRACTOR

an adder/subtractor circuit ,as the name indicates ,is able to perform addition as well as subtraction.Here ,I used 4 bit addition and subtraction units together.(Such a circuit is available in the market. It is 7483).Here ,I have a control signal as input ,in addition to the conventional inputs.Here,when the control signal is '0' addition takes place.When control signal is '1',subtraction takes place.The control signal is represented as ADD_SB.Now consider the logic diagram shown below.If you are not familiar with the design of this circuit,please refer any standard text book of Digital Electronics.



Now consider the VHDL code
--FIRST START WITH A FULL ADDER
--THEN DESIGN XOR GATE
--THEN BIND 4 FULL ADDERS AND 4 XOR GATES
--PURE STRUCTURAL MODELING
--MIXED OR BEHAVIORAL ALSO CAN BE USED
--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;
--I AM GOING TO DESIGN AN ENTITY FOR XOR FUNCTION
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XOR_1 IS
PORT(A,B:IN STD_LOGIC;Y:OUT STD_LOGIC);
END XOR_1;
ARCHITECTURE BEHV OF XOR_1 IS
BEGIN
Y<=A XOR B;
END BEHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADD_SUB IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);AD_SB:IN STD_LOGIC;SUM_DIF:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT :OUT STD_LOGIC);
END ADD_SUB;
ARCHITECTURE BEH123 OF ADD_SUB IS
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C_TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
XOR1:ENTITY WORK.XOR_1 PORT MAP(B(0),AD_SB,TEMP(0));
XOR2:ENTITY WORK.XOR_1 PORT MAP(B(1),AD_SB,TEMP(1));
XOR3:ENTITY WORK.XOR_1 PORT MAP (B(2),AD_SB,TEMP(2));
XOR4:ENTITY WORK.XOR_1 PORT MAP (B(3),AD_SB,TEMP(3));
-- INV1:ENTITY WORK.INV PORT MAP (AD_SB,CTRL);
--ADDER:ENTITY WORK.ADDER_4BIT PORT MAP(A,TEMP,SUM,COUT);
FA1:ENTITY WORK.FA PORT MAP (A(0),TEMP(0),AD_SB,SUM_DIF(0),C_TEMP(0));
FA2:ENTITY WORK.FA PORT MAP (A(1),TEMP(1),C_TEMP(0),SUM_DIF(1),C_TEMP(1));
FA3:ENTITY WORK.FA PORT MAP (A(2),TEMP(2),C_TEMP(1),SUM_DIF(2),C_TEMP(2));
FA4:ENTITY WORK.FA PORT MAP (A(3),TEMP(3),C_TEMP(2),SUM_DIF(3),COUT);
END BEH123;

VHDL MODEL OF SUBTRACTOR

Subtraction can be implemented by adder.2's complement addition is same as that of subtraction.I already discussed the 4 bit parallel adder,so I am skipping that discussion here.In addition to that circuit,we need a 2's complement conversion of the number to be subtracted.Remember,this is not the easiest way to implement subtraction. If you are familiar with various packages available in VHDL library,you can use it here. This code is to understand structural style of modeling(or the low level modeling principles).

The VHDL code is shown below

--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;
-- NOW DESIGN A 4 BIT ADDING UNIT BY CASCADING 4 FULL ADDER UNITS
--STRUCTURAL BINDING OF UNITS ENTITY FA
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADDER_4BIT IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);C:OUT STD_LOGIC);
END ADDER_4BIT;
ARCHITECTURE BEHV OF ADDER_4BIT IS
SIGNAL TEMP:STD_LOGIC:='0';
SIGNAL CAR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
FA1:ENTITY WORK.FA PORT MAP(A(0),B(0),TEMP,S(0),CAR(0));
FA2:ENTITY WORK.FA PORT MAP(A(1),B(1),CAR(0),S(1),CAR(1));
FA3:ENTITY WORK.FA PORT MAP(A(2),B(2),CAR(1),S(2),CAR(2));
FA4:ENTITY WORK.FA PORT MAP(A(3),B(3),CAR(2),S(3),C);
END BEHV;

--NOW I AM GOING TO DEVELOP A 4 BIT SUBSTRACTOR
--2'S COMPLEMENT ADDITION IS USING
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--TO USE "+" FUNCTION
ENTITY SUB_4BIT IS
PORT(AIN,BIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);DIFF:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);BOR:OUT STD_LOGIC);
END SUB_4BIT;
ARCHITECTURE BEH OF SUB_4BIT IS
SIGNAL TEMP,TEMP1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
TEMP<=NOT BIN;
TEMP1<=TEMP+"0001";
ADDERUNIT:ENTITY WORK.ADDER_4BIT PORT MAP(AIN,TEMP1,DIFF,BOR);
END BEH;

VHDL MODEL OF 4 BIT PARALLEL BINARY ADDER

A 4 bit binary parallel adder can be formed by cascading four full adder units.The carry of each stage is connected to the next unit as the carry in (That is the third input).Similarly we can make 8 bit adder.Remember 8 bit adder is a significant design ,because we need it in processor design as part of ALU.(There is no need to use this structural style model there.Instead, we can use the packages available in VHDL directly).A simple logic diagram of 4 bit parallel binary adder is given below.



The VHDL code of 4 bit parallel adder is given below

--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;
-- NOW DESIGN A 4 BIT ADDING UNIT BY CASCADING 4 FULL ADDER UNITS
--STRUCTURAL BINDING OF UNITS ENTITY FA
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADDER_4BIT IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);C:OUT STD_LOGIC);
END ADDER_4BIT;
ARCHITECTURE BEHV OF ADDER_4BIT IS
SIGNAL TEMP:STD_LOGIC:='0';
SIGNAL CAR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
FA1:ENTITY WORK.FA PORT MAP(A(0),B(0),TEMP,S(0),CAR(0));
FA2:ENTITY WORK.FA PORT MAP(A(1),B(1),CAR(0),S(1),CAR(1));
FA3:ENTITY WORK.FA PORT MAP(A(2),B(2),CAR(1),S(2),CAR(2));
FA4:ENTITY WORK.FA PORT MAP(A(3),B(3),CAR(2),S(3),C);
END BEHV;
--getting output properly
--DIRECT INSTANTIATION IS USED

VHDL MODEL OF FULL ADDER

A full adder has 3 single bit inputs and two single bit outputs.The outputs are sum and carry respectively.From truth table ,we can obtain the logic expression for the sum and carry output.Here I used the logic expressions.We can also use structural style of modeling by using gates.



The VHDL code of full adder unit is shown below.

--PREPARED BY BIJOY
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC);
END FA;
ARCHITECTURE BEHV OF FA IS
BEGIN
SUM<=A XOR B XOR CIN;
COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN);
END BEHV;

VHDL MODEL OF 8:1(8 INPUT) MULTIPLEXER

Multiplexer is simply a data selector.It has multiple inputs and one output.Any one of the input line is transferred to output depending on the control signal.This type of operation is usually referred as multiplexing .In 8:1 multiplexer ,there are 8 inputs.Any of these inputs are transferring to output ,which depends on the control signal.For 8 inputs we need ,3 bit wide control signal .

Working:If control signal is "000" ,then the first input is transferring to output line.If control signal is "111",then the last input is transferring to output.Similarly for all values of control signals.A simple block diagram of 8:1 multiplexer is shown here.



Now see the VHDL code of 8:1 multiplexer

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX8_1 IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC);
END MUX8_1;
ARCHITECTURE BEH123 OF MUX8_1 IS
BEGIN
PROCESS(DIN,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN(0);
WHEN"001"=>DOUT<=DIN(1);
WHEN"010"=>DOUT<=DIN(2);
WHEN"011"=>DOUT<=DIN(3);
WHEN"100"=>DOUT<=DIN(4);
WHEN"101"=>DOUT<=DIN(5);
WHEN"110"=>DOUT<=DIN(6);
WHEN"111"=>DOUT<=DIN(7);
WHEN OTHERS=>
DOUT<='Z';
END CASE;
END PROCESS;
END BEH123;

VHDL MODEL OF SERIAL IN PARALLEL OUT SHIFT REGISTER(SERIAL TO PARALLEL CONVERTER)

We have already discussed about Parallel to Serial converter.Now I am going to design a Serial in Parallel out shift register (or Serial to Parallel converter).It is also a shift right type shift register.D flip flops are the basic building blocks of this circuit.It is an 8 bit shift register,and so we need 8 D flip flops cascaded together.
We already discussed about D flip flops.So now, consider the VHDL code.here I have not designed a register to store the serial information.So you have to apply the serial input bit by bit after each clock pulse.


--CODE OF D FLIP FLOP

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF_1 IS
PORT(D,CLOCK:IN STD_LOGIC;Q,QBAR:OUT STD_LOGIC);
END DFF_1;
ARCHITECTURE FF OF DFF_1 IS
BEGIN
PROCESS(D,CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
Q<=D;
QBAR<=NOT D;
END IF;
END PROCESS;
END FF;

--SUCCESS GETTING OUTPUT
--NOW DESIGN SHIFT REGISTER
--SERIAL TO PARALLEL CONVERTER AND SERIAL IN PARALLEL OUT SHIFT REGISTER ARE --BASICALLY SAME
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SERTOPAR IS
PORT(SERIN,CLOCK:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END SERTOPAR;
ARCHITECTURE BE1 OF SERTOPAR IS
SIGNAL S1,S2,S3,S4,S5,S6,S7,S8:STD_LOGIC;
BEGIN
D1:ENTITY WORK.DFF_1 PORT MAP(SERIN,CLOCK,S1,OPEN);
Q(0)<=S1;
D2:ENTITY WORK.DFF_1 PORT MAP(S1,CLOCK,S2,OPEN);
Q(1)<=S2;
D3:ENTITY WORK.DFF_1 PORT MAP (S2,CLOCK,S3,OPEN);
Q(2)<=S3;
D4:ENTITY WORK.DFF_1 PORT MAP (S3,CLOCK,S4,OPEN);
Q(3)<=S4;
D5:ENTITY WORK.DFF_1 PORT MAP (S4,CLOCK,S5,OPEN);
Q(4)<=S5;
D6:ENTITY WORK.DFF_1 PORT MAP (S5,CLOCK,S6,OPEN);
Q(5)<=S6;
D7:ENTITY WORK.DFF_1 PORT MAP (S6,CLOCK,S7,OPEN);
Q(6)<=S7;
D8:ENTITY WORK.DFF_1 PORT MAP (S7,CLOCK,Q(7),OPEN);
END BE1;
--working properly
--CREATED AND TESTED BY BIJOY
--DATE IS 14/08/2009

MODEL OF D FLIP FLOP

Flip flops are memory elements,which can store a bit.D flip flop is useful in designing counters,shift registers etc.Here D stands for data.It is a synchronous circuit.So it need a clock signal for working.A simple block diagram of D flip flop is shown below.it will help you to understand the list of inputs and outputs needed for the operation of it.




The inputs needed for operation are:
1)D :This input is the actual data input to the flip flop.
2)CLOCK :This is the clock needed for all synchronous circuits.
The outputs needed are:
1)Q :This is the first output of D flip flop.On the active edge of clock(for edge triggered flip flops) the D input is transferring to this output pin.
2)QBAR :This gives the complement of Q.

Working: In my design ,I developed a positive edge triggered flip flop. That is,the D input is transferring to Q during the '0' to '1' (or low to high)transition of CLOCK> If you need a negative edge triggered flip flop ,you can edit this code by replacing RISING_EDGE(CLOCK) by FALLING_EDGE(CLOCK).

VHDL CODE OF D FLIP FLOP

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF_1 IS
PORT(D,CLOCK:IN STD_LOGIC;Q,QBAR:OUT STD_LOGIC);
END DFF_1;
ARCHITECTURE FF OF DFF_1 IS
BEGIN
PROCESS(D,CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
Q<=D;
QBAR<=NOT D;
END IF;
END PROCESS;
END FF;
--IT IS WORKING PROPERLY