VHDL MODEL OF SERIAL IN PARALLEL OUT SHIFT REGISTER(SERIAL TO PARALLEL CONVERTER)

We have already discussed about Parallel to Serial converter.Now I am going to design a Serial in Parallel out shift register (or Serial to Parallel converter).It is also a shift right type shift register.D flip flops are the basic building blocks of this circuit.It is an 8 bit shift register,and so we need 8 D flip flops cascaded together.
We already discussed about D flip flops.So now, consider the VHDL code.here I have not designed a register to store the serial information.So you have to apply the serial input bit by bit after each clock pulse.


--CODE OF D FLIP FLOP

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF_1 IS
PORT(D,CLOCK:IN STD_LOGIC;Q,QBAR:OUT STD_LOGIC);
END DFF_1;
ARCHITECTURE FF OF DFF_1 IS
BEGIN
PROCESS(D,CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
Q<=D;
QBAR<=NOT D;
END IF;
END PROCESS;
END FF;

--SUCCESS GETTING OUTPUT
--NOW DESIGN SHIFT REGISTER
--SERIAL TO PARALLEL CONVERTER AND SERIAL IN PARALLEL OUT SHIFT REGISTER ARE --BASICALLY SAME
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SERTOPAR IS
PORT(SERIN,CLOCK:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END SERTOPAR;
ARCHITECTURE BE1 OF SERTOPAR IS
SIGNAL S1,S2,S3,S4,S5,S6,S7,S8:STD_LOGIC;
BEGIN
D1:ENTITY WORK.DFF_1 PORT MAP(SERIN,CLOCK,S1,OPEN);
Q(0)<=S1;
D2:ENTITY WORK.DFF_1 PORT MAP(S1,CLOCK,S2,OPEN);
Q(1)<=S2;
D3:ENTITY WORK.DFF_1 PORT MAP (S2,CLOCK,S3,OPEN);
Q(2)<=S3;
D4:ENTITY WORK.DFF_1 PORT MAP (S3,CLOCK,S4,OPEN);
Q(3)<=S4;
D5:ENTITY WORK.DFF_1 PORT MAP (S4,CLOCK,S5,OPEN);
Q(4)<=S5;
D6:ENTITY WORK.DFF_1 PORT MAP (S5,CLOCK,S6,OPEN);
Q(5)<=S6;
D7:ENTITY WORK.DFF_1 PORT MAP (S6,CLOCK,S7,OPEN);
Q(6)<=S7;
D8:ENTITY WORK.DFF_1 PORT MAP (S7,CLOCK,Q(7),OPEN);
END BE1;
--working properly
--CREATED AND TESTED BY BIJOY
--DATE IS 14/08/2009