MODEL OF A 256 BYTE RAM

RAM is the Random Access Memory.The user can access this memory chip randomly. In other words ,it is a read write memory. In my design ,I selected the following inputs for my RAM
a)CS
This is the chip select. In my code active high chip select is used.
b)RW
This is the read/write signal for RAM. For writing ,I selected ‘1’ , and ‘0’ for reading.
c)ADDR
This is the address bus . Here I designed a 256 byte RAM.So 8 bit address bus is needed.
d)DIN
This is the Data in pin.It is 8 bit wide.
e)CLOCK
This input is meant to give the clock signal to RAM.

In addition to these,RAM needes an 8 bit wide output port for outputing the data. If the DIN is a bidirectional one,there is no need for this separate port.
Now see the block diagram and code of the RAM




VHDL CODE OF 256 BYTE RAM

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RAM IS
PORT(CLOCK,RW,CS:IN STD_LOGIC;ADDR:IN STD_LOGIC_VECTOR (7 DOWNTO 0);DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END RAM;
ARCHITECTURE BEH12 OF RAM IS
TYPE RAM_12 IS ARRAY (0 TO 255)OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL RAM_PTR:RAM_12;
--prepared by BIJOY
BEGIN
PROCESS(CLOCK,RW,CS)
BEGIN
IF CS='1'THEN
IF RISING_EDGE(CLOCK) THEN
IF RW='1' THEN
RAM_PTR(CONV_INTEGER(ADDR))<=DIN;
ELSE
DOUT<=RAM_PTR(CONV_INTEGER(ADDR));
END IF;
END IF;
ELSE
DOUT<="ZZZZZZZZ";
END IF;
END PROCESS;
END BEH12;
--getting output