CODE STRUCTURE OF VHDL

Every VHDL code contains at least 3 parts. They are

1 )Library Declaration

2)Entity Declaration

3)Architecture body

Let us discuss these parts in brief

1)LIBRARY DECLERATION

VHDL itself contains a number of libraries. By declaring that libraries in our code, it it is possible to use the items in the library ,in our code. Each library there are a lot of packages. We can specify the name of the package after the library declaration .Consider the code segment shown below.

library ieee;

use ieee.std_logic_1164.all;

In this segment ‘ieee ‘ is the library we declared.The second statement calls the ‘std_logic_1164’package in IEEE.This package contains a set of useful functions like ‘and’ and some data types . So instead of creating these functions ,designer can directly use the predefined functions.

2 )ENTITY DECLARATION

Entity declaration is the overview of the system to be designed. In entity declaration designer only specifies the inputs and outputs the system has.

entity and_1 is

port(a,b:in std_logic;y:out std_logic);

end and_1;

If any of the inputs or outputs are more than one bit length,then it is possible to declare it as vector.

Consider the example:

entity mux8_1 is

port(din:in std_logic_vector(7 downto 0);sel:in std_logic_vector(2 downto 0);dout:out std_logic);

end mux8_1;

Here the input din is 8 bit wide.

3)ARCHITECTURE BODY

It is the part of the code,where the architecture of the entity is specified.For this purpose,different modeling styles are using.We will see the different modeling styles later.A simple architecture is shown here ,to illustrate the synatax.

architecture behv of and_1 is

begin

y<=a and b;

end behv;

Now the entire code structure is shown below,through the example of an AND gate.

library ieee;

use ieee.std_logic_1164.all;

entity and_1 is

port(a,b:in std_logic;y:out std_logic);

end and_1;

architecture behv of and_1 is

begin

y<=a and b;

end behv;

--code is complete

--Prepared by BIJOY