Working:If control signal is "000" ,then the first input is transferring to output line.If control signal is "111",then the last input is transferring to output.Similarly for all values of control signals.A simple block diagram of 8:1 multiplexer is shown here.
Now see the VHDL code of 8:1 multiplexer
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX8_1 IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC);
END MUX8_1;
ARCHITECTURE BEH123 OF MUX8_1 IS
BEGIN
PROCESS(DIN,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN(0);
WHEN"001"=>DOUT<=DIN(1);
WHEN"010"=>DOUT<=DIN(2);
WHEN"011"=>DOUT<=DIN(3);
WHEN"100"=>DOUT<=DIN(4);
WHEN"101"=>DOUT<=DIN(5);
WHEN"110"=>DOUT<=DIN(6);
WHEN"111"=>DOUT<=DIN(7);
WHEN OTHERS=>
DOUT<='Z';
END CASE;
END PROCESS;
END BEH123;
11 comments:
cant run code
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
Port ( x:in STD_LOGIC_VECTOR (7 downto 0);
sel:in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process (x,sel)
begin
case sel is
when "000"=>y<=x(0);
when "001"=>y<=x(1);
when "010"=>y<=x(2);
when "011"=>y<=x(3);
when "100"=>y<=x(4);
when "101"=>y<=x(5);
when "110"=>y<=x(6);
when "111"=>y<=x(7);
when others=> null;
end case;
end process;
nd Behavioral;
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_multiplexer_vhd IS
END tb_multiplexer_vhd;
ARCHITECTURE behavior OF tb_multiplexer_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer
PORT(
x:IN std_logic_vector(7 downto 0);
sel:IN std_logic_vector(2 downto 0);
y:OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL x : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL sel : std_logic_vector(2 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer PORT MAP(x => x,
sel => sel,
y => y
);
x<= "01010101" after 10ns;
sel<= "001" after 10ns,"010" after 20ns,"011" after 30ns,"100" after 40ns,"101" after 50ns,"110" after 60ns, "111" after 70ns;
END;
heyy , how to run testbench ?? reply pls
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What would be the code if we were to design a multiplexer with 2 eight bit inputs controlled by one bit integer. Please reply?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_8to1 is
port(
A,B,C,D,E,F,G,H : in bit;
S0,S1,S2 : in bit;
Z: out bit
);
end mux_8to1;
architecture bhv of mux_8to1 is
begin
process (A,B,C,D,E,F,G,H,S0,S1,S2) is
begin
if (S0 ='0' and S1 = '0' and S2 = '0') then
Z <= A;
elsif (S0 ='0' and S1 = '0' and S2 = '1') then
Z <= B;
elsif (S0 ='0' and S1 = '1' and S2 = '0') then
Z <= C;
elsif (S0 ='0' and S1 = '1' and S2 = '1') then
Z <= D;
elsif (S0 ='1' and S1 = '0' and S2 = '0') then
Z <= E;
elsif (S0 ='1' and S1 = '0' and S2 = '1') then
Z <= F;
elsif (S0 ='1' and S1 = '1' and S2 = '0') then
Z <= G;
else
Z <= H;
end if;
end process;
end bhv;
Truth table plz
Truth table where?
Can any one write a structural style code for 8 to 1 mux
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX8_1 IS
PORT ( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A,B,C,D,E,F,G,H :IN STD_LOGIC;
MUX_OUT: OUT STD_LOGIC );
END MUX8_1;
ARCHITECTURE BEHAVIORAL OF MUX8_1 IS
BEGIN
PROCESS (SEL,A,B,C,D,E,F,G,H)
BEGIN
CASE SEL IS
WHEN "000" => MUX_OUT <= A;
WHEN "001" => MUX_OUT <= B;
WHEN "010" => MUX_OUT <= C;
WHEN "011" => MUX_OUT <= D;
WHEN "100" => MUX_OUT <= E;
WHEN "101" => MUX_OUT <= F;
WHEN "110" => MUX_OUT <= G;
WHEN "111" => MUX_OUT <= H;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END BEHAVIORAL;
Where is the test bench wave form bro
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