VHDL MODEL OF PARALLEL TO SERIAL CONVETER

This is the model of a parallel to serial converter .This circuit is very much useful in designing a microprocessors and microcontrollers.In processor,data is in parallel format.But sometimes we need data as bit by bit(Example :To transfer data from processor through serial bus).So it is very useful.

Simply a parallel to serial converter consists of
a)An 8 bit multiplexer,
b)A 3 bit counter.

A simplified logic diagram of the circuit is shown here.



Working:The parallel data is applied at the input of multiplexer.The select input of the multiplexer is connected to the output of the 3 bit counter.As the count increases the select input of the multiplexer changes,and hence each of the parallel inputs are connected to single output line of multiplexer.Thus parallel to serial conversion takes place.Here I used a simple behavioral code for the counter.In stead of this code ,you can use your own design.

VHDL CODE
It consists of 3 parts:1)Code for 8:1 multiplexer , 2)Code for 3 bit counter, and 3)Structural binding of (1) and (2).The code is shown below.Remember,the port name of last entity is shown in the logical diagram.

--PREPARED BY BIJOY
--FIRST DESIGN A MUX
--THEN A 3 BIT COUNTER
--LAST CASCADE THEM
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX8_1 IS
PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC);
END MUX8_1;
ARCHITECTURE BEH123 OF MUX8_1 IS
BEGIN
PROCESS(DIN,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN(0);
WHEN"001"=>DOUT<=DIN(1);
WHEN"010"=>DOUT<=DIN(2);
WHEN"011"=>DOUT<=DIN(3);
WHEN"100"=>DOUT<=DIN(4);
WHEN"101"=>DOUT<=DIN(5);
WHEN"110"=>DOUT<=DIN(6);
WHEN"111"=>DOUT<=DIN(7);
WHEN OTHERS=>
DOUT<='Z';
END CASE;
END PROCESS;
END BEH123;
--NOW DEVELOP A COUNTER
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER_123 IS
PORT(CLOCK:IN STD_LOGIC;QOUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COUNTER_123;
ARCHITECTURE BEH OF COUNTER_123 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
PROCESS(CLOCK)
-- VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
IF RISING_EDGE(CLOCK)THEN
TEMP<=TEMP+"001";
END IF;
--QOUT<=TEMP;
END PROCESS;
QOUT<=TEMP;
END BEH;
--NOW BINDING OF THIS COMPONENTS


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PAR_SER IS
PORT(DIN_1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CLK:IN STD_LOGIC;DOUT_1:OUT STD_LOGIC);
END PAR_SER;
ARCHITECTURE BEH_12 OF PAR_SER IS
SIGNAL QOUT_1:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--STRUCTURAL STYLE OF MODELLING IS USED TO BIND THE INDIVIDUAL COMPONENTS
COUNTER:ENTITY WORK.COUNTER_123 PORT MAP(CLK,QOUT_1);
MUX:ENTITY WORK.MUX8_1 PORT MAP(DIN_1,QOUT_1,DOUT_1);
END BEH_12;